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The Hype, Myths, and Realities of Testing 2.5D/3D Integrated Circuits
时间:2017-09-14 11:54    点击:   所属单位:通信工程学院
讲座名称 The Hype, Myths, and Realities of Testing 2.5D/3D Integrated Circuits
讲座时间 2017-09-18 10:00:00
讲座地点 北校区新科技楼1012会议室
讲座人 Prof. Krishnendu Chakrabarty
讲座人介绍 Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering and Professor of Computer Science at Duke University. He is also the chair of the Department of Electrical and Computer Engineering. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the IEEE Computer Society Technical Achievement Award, and 11 best papers awards at leading IEEE conferences.  His current research projects include: testing and design-for-testability of integrated circuits and systems; digital microfluidics, biochips, and cyberphysical systems; resilient computing systems; enterprise system optimization and smart manufacturing. Prof. Chakrabarty holds a Ph.D. from the University of Michigan and is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). Currently he serves as Editor-in-Chief of IEEE Transactions on VLSI Systems (2015-2016). He is an Editor of the Journal of Electronic Testing: Theory and Applications (JETTA), and an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Computers, IEEE Transactions on Multiscale Computing Systems, and IEEE Transactions on Biomedical Circuits and Systems.
讲座内容 Despite the numerous benefits offered by 2.5D/3D integration, testing remains a major obstacle that hinders its widespread adoption. Concerns related to test cost, yield and reliability continue to derail the commercial exploitation of 2.5D/3D ICs. Test techniques and design-for-testability (DfT) solutions are now being explored in the research community, with considerable focus on wafer probing, pre-bond test of passive interposers, test access to modules in stacked dies, cost modeling, and the targeting of new defect types. In this talk, the speaker will examine the hype, myths, and realities of 2.5D/3D ICs. He will reflect on some of the over-hyped claims and expose the myths that have been exposed in recent years. He will present a reality-check on testing and DfT challenges, and describe some of the recent solutions being advocated for these challenges. The key questions to be addressed are: “What to Test? How to Test? When to Test?” To answer these questions, the presentation will cover pre-bond testing of TSVs and interposers, DfT solutions and optimization for stack testing, and test-flow selection. The speaker will also describe recent efforts at understanding defects and test challenges in monolithic 3D integrated circuits.
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