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Hardware Architecture and VLSI Design for Wireless Communication System
时间:2017-08-04 17:15    点击:   所属单位:通信工程学院
讲座名称 Hardware Architecture and VLSI Design for Wireless Communication System
讲座时间 2017-08-10 10:00:00
讲座地点 北校区新科技楼1012会议室
讲座人 Prof. Xinming Huang
讲座人介绍 Xinming Huang is a Professor in the Department of Electrical and Computer Engineering at the Worcester Polytechnic Institute (WPI) and Director of the Embedded Computing and Intelligence Lab. WPI is located in the suburb of Boston. It was established in 1865 and was the third oldest engineering universities in the US. The university is ranked 60 among all national research universities by US News & World Report in 2017. Dr. Huang received his PhD in electrical engineering from Virginia Tech in 2001. After that, he joined the Bell Labs of Lucent Technologies as a Member of Technical Staff with the wireless advanced technology laboratory. He was a recipient of the Central Bell Labs annual excellence award, IBM faculty, DARPA young faculty award, IEEE HKN outstanding professor award, and WPI faculty achievement award. His main interests are in the areas of hardware architecture for wireless communications, error correction coding, information security, computer vision and deep learning. He is also an expert on cyber-physical systems for autonomous vehicles and smart health. He has over 100 publications on IEEE transactions and top conferences.
讲座内容 Wireless communications have been growing exponentially and become ubiquitous in the past two decades. Semiconductor technology is the driving force behind these low-power high-performance devices, such as smartphones, tablets and Internet-of-Things. In this talk, we will discuss the design of three key components in a wireless communication system, including receiver, synchronization, and error correction coding. The receiver is to detect the symbols from the received signal which has additive noise through the channel. Synchronization includes carrier frequency offset and timing recover. Forward error correction coding (FEC) is employed to improve the bit-error-rate (BER). For MIMO systems, we will present the hardware architecture and FPGA implementations of maximum-likelihood detector, frequency and timing synchronization, and interference alignment. For FEC, we will present the VLSI design of high-throughput and rate-compatible low-density parity-check (LDPC) decoders. In addition, we will brief discuss the model-based design for FPGA-based software defined radio. Our research goal is to transform advanced signal processing and communication algorithms into low-power integrated circuits that can meet the real-time throughput and performance requirement.
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