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IEEE固态和集成电路技术国际会议
时间:2012-08-28 20:49    点击:   所属单位:其它
【会议基本信息】
会议名称(中文) IEEE固态和集成电路技术国际会议
会议名称(英文) IEEE International Conference on Solid-State
所属学科 集成电路
会议类型 国际会议
会议论文集是否检索
开始日期 2012-11-29
结束日期 2012-12-01
所在国家 China
所在城市 Xi'an
具体地点
主办单位 IEEE Beijing Section
协办单位 IET
会议议题
【组织结构】
会议主席 T. P. Ma
组织委员会主席
程序委员会主席
会议嘉宾
【重要日期】
摘要截稿日期 2012-07-15
论文录用通知日期 2012-08-15
【会务组联系方式】
联系人 Dr. Yu-Long Jiang
联系电话 86-21-65643768
E-mail icsict@fudan.edu.cn
通讯地址 Department of Microelectronics Fudan University
邮政编码
会议注册费
会议网站 http://www.icsict.com
会议背景介绍
The IEEE ICSICT-2012 conference is the 11th in the series aiming to provide an international forum for the presentation and discussion of recent advances in solid-state and integrated circuit technology. The conference will be held on Oct.29-Nov.1, 2012 in Xi’an, China. All aspects of solid-state devices, circuits, processing technologies, materials and other related research are within the scope of the conference. The three days of contributed and invited presentations on the latest developments in diverse fields given in oral and poster sessions, panel discussions on leading edge technology issues, and other activities will provide extensive opportunities for technical information exchange as well as a stimulating environment for mutual communication among participants. An exhibition of equipment and materials for solid state and integrated circuit technologies will be held concurrently with the conference. In addition, there will be discussions devoted to opportunities for cooperation and joint ventures in the microelectronics business in China. Excellent Student Paper Award will be presented at the closing of the conference.
 
征文范围及要求 The Scope and Topics of the Conference
(Papers are solicited in, but not limited to the following areas)
 
Process & Device Technologies
1.       Channel Engineering
2.       High-k/Metal gate Technology
3.       Advanced Source/Drain Technology
4.       Interconnect Technology
5.       Advanced 3D Integration
6.       Novel Process Technologies
7.       Ultra-Thin Body Transistors and Device Variability
8.       Advanced High-k Metal Gate SoC and High Performance CMOS Platforms
9.       CMOS Performance Enhancing and Novel Devices
10.      Advanced FinFETs and Nanowire FETs
11.      CNT, MTJ Devices and Nanowire Photodiodes
12.      Low- Power and Steep Slope Switching Devices
13.      Graphene Devices
14.      Advanced Technologies for Ge MOSFETs
15.      Organic semiconductor devices and technologies
16.      Compound semiconductor devices and Technology
17.      Ultra High Speed Transistors, HEMT/HBT etc. 
18.      Advanced Power Devices and Reliability
19.      Flash Memory
20.      IT Magnetic RAM
21.      Resistive RAMs
22.      Phase Change Memory
23.      3-Dimensional Memory
24.      MEMS Technology
25.      Thin Film Transistors
26.      Biosensors
27.      PV and Energy Harvesting
28.      Front End of Line (FEOL) Reliability
29.      Memory Reliability
30.      Back-End of Line and ESD Reliability
31.      High-Frequency and Multi-Gate Device & Modeling
32.      Advanced Device Performance and Variation Modeling
33.      Simulation of Memory Devices
34.      Simulation of Non-Silicon Materials and Devices
 
Circuits & ICCAD
35.      Processors
36.      Analog Circuits
37.      SOC
38.      PLL and CDR
39.      Low-Power Nyquist ADCs
40.      Digital Circuits Resilient
41.      High-Resolution and High Speed Data Converters
42.      Digital Chip-to-Chip and On-Die Interfaces
43.      Advanced Clock Generation
44.      Clocking Building Blocks
45.      High Speed On-Die Network Processor Clocking
46.      Advanced SRAM & DRAM Circuits, Embbeded Memorres
47.      Nonvolatile Memories Circuits
48.      Advanced Transceivers Techniques
49.      RF and New Wireless Transceivers
50.      RF Circuits and Systems
51.      Interference Robust RF Receivers
52.      Signal Processing for Wireless
53.      System-Level Modeling & Simulation/Verification
54.      System-Level Synthesis & Optimization
55.      High-Level/Behavioral/Logic Synthesis & Optimization
56.      Physical Design
57.      DFM 
 
Paper Submission
Prospective authors are requested to submit 3 pages camera-ready full length paper in English for proceedings publication. The proceedings will have an IEEE catalogue number and will be collected in IEEE publication database ---- IEEE X’ploreÒ.
 
Deadline for Camera-Ready Full-Length Paper Submission: July 15, 2012
Notification of Acceptance: August. 15, 2012
On-line submission at web-site http://www.icsict.com is required.
 
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